In this work, we discuss a family of parallel implicit time integrators for multicore and potentially multi-node or multi-gpgpu systems. The method is an extension of Revisionist Integral Deferred Correction (RIDC) by Christlieb, Macdonald and Ong (SISC- 2010) which constructed parallel explicit time integrators. The key idea is to re-write the defect correction framework so that, after initial startup costs, each correction loop can be lagged behind the previous correction loop in a manner that facilitates running the predictor and correctors in parallel. In this paper, we show that RIDC provides a framework to use p cores to generate a pth-order implicit solution to an initial value problem (IVP) in approximately the same wall clock time as a single core, backward Euler implementation (p ≤ 12). The construction, convergence and stability of the schemes are presented, along with supporting numerical evidence.

VL - 46 IS - 1 ER -